<dlan>
apritzel: I'd say, it's very useful! any possible to add a "state" command, to just retrieve gpio current status without actually set or write gpio registers
<apritzel>
dlan: that's what "input" does
<apritzel>
it output 0 or 1
<dlan>
let me think, it's probably enough..
<dlan>
it only read data reg,, I thought also to print the gpio output or input info
<dlan>
btw, does sunxi-fel or u-boot support spi flash with spif IP (spi flash controller) or just the generic spi controller?
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<wens>
apritzel: I'm looking at the a523 ccu code, and for the pll's there's an input divider defined, but it's not in the datasheet?
<apritzel>
wens: they are mentioned in the A523 user manual, and I think someone mentioned they are in the BSP as well
<apritzel>
dlan: do you mean to print the configuration, so whether a particular pin is configured as input or output?
<dlan>
yes, print the configuration, so know currently it's in input or output mode, the use case I can think of, use sunxi-fel to check when return FEL from SPL
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<wens>
apritzel: the periph plls don't have a divider
<wens>
the base pll that is
<apritzel>
wens: which ones, exactly?
<wens>
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */ # this setting seems to be bogus across the board
<wens>
I'm looking at a523 manual v1.4, and none of the PLLs have anything defined in bit 1
<apritzel>
both PLL_PERI0 and PLL_PERI1 mention bit 1 as an input divider in the A523 manual v1.2
<apritzel>
this is the time where the people with those oscilloscopes can shine (HINT HINT)
<apritzel>
the CLK_FANOUT pins can use a divided-down source from PLL_PERI0 as their source
<apritzel>
probably best done in U-Boot: "mw.l 0x2001f3c 0x00e000a7"
<apritzel>
should enable all three fanout clocks, at different frequencies
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<apritzel>
well, it's only FANOUT0 exposed on PH16, which is connected to the PHY
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<apritzel>
actually there is a much simpler way to check this, and I think I even tried this before: since MMC0 is clocked by PLL_PERI0, the read performance from an SD card should change when flipping bit 1
<wens>
also , I see a couple (memory related) clocks that use MP but have "no P"
<wens>
seems a bit weird
<paulk>
apritzel: yes gpio support is very nice!
<paulk>
apritzel: btw not sure you saw it yesterday, there's a new a133 board with proper schematics available
<paulk>
and friendlier connectors compared to the liontron's jst ones
<paulk>
and they also sell a lvds display for it
<apritzel>
yeah, saw it, thanks, but the A133 is just "meh", if you ask me, so not super excited about it, sorry!
<apritzel>
wens: any particular reasons for those clock checks? Is that about the eMMC? I did check the clocks already (that's how I found the 800MHz issue)
<apritzel>
and at least with SD cards I could confirm they are right: I got the expected 23 MB/s, and tweaking some clock bits gave me the expected doubling/halving of read performance
<paulk>
apritzel: yes I get it, but I think it has a future for industrial applications and there's lots of low-hanging fruits
<apritzel>
sure, I was about to order proper connectors for the Liontron board, to test (and enable) SPI and other missing peripherals
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<wens>
apritzel: I'm writing the mcu clock driver and using the ccu driver as a reference for macros and stuff
<apritzel>
ah, nice one, many thanks!
<apritzel>
wens: and yeah, writing clock drivers for Allwinner, with newly found bits, hacks, and patchy documentation is always fun!
<wens>
apritzel: yeah, there's a couple clocks that aren't in the manual, and there's also no information for their users (such as dsp or tzma)
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<wens>
blah, rtc seems driven by internal osc by default
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<BroderTuck>
wens: yeah, the android boot log from my h728 tv box has this message: "sunxi:rtc-7090000.rtc:[WARN]: Warning: Using internal RC 16M clock source. Time may be inaccurate!"
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<apritzel>
wens: yes, confirmed: if I set bit 1 in the PLL_PERI0 register, SD card read speed exactly halves, so M1 is a thing. Bit 0 has no effect.
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