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19:30
<
apritzel >
interesting: the A523 has a 4th undocumented CPU PLL (at offset 0x0), which the two clusters can be muxed to. This could be used as an intermittent clocksource while re-locking the original PLL during DVFS
19:31
<
apritzel >
although both clusters also have PLL_PERI0-600M in their mux list, which sounds like a safer choice
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21:51
<
wens >
apritzel: do you remember where you got the sdm parameters for audio-pll0?
21:56
<
apritzel >
wens: you can find some in BSP sources, but for pattern that's just the fraction of 131072 in the lower bits to add to the factor, plus bits 30&31 set
21:57
<
wens >
radxa's bsp seems to have better values resulting in exact multiples of 24.576 and 22.5792
21:59
<
apritzel >
so { .rate = 90316800, .pattern = 0xc000872b, .m = 20, .n = 75 } goes like: 90316800 * 20 / 24MHz = 75.264 => 75 + 0x872b/131072
22:01
<
apritzel >
I used a spreadsheet to calculate the values with the smallest errors
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22:03
<
apritzel >
but 22.5792 MHz * 4 is exactly 90316800? Same with 24.576M * 4
22:04
<
wens >
nevermind, I might have mistyped something
22:05
<
wens >
however it seems before the post divider, the PLL has to be at least 1.18 GHz, so .n = 49 seems borderline?
22:06
<
wens >
blah, clk is somehow not picking the exact rate with SDM, instead getting 98285714
22:11
<
apritzel >
I could offer m=22, n=90, bottom=14680, that's has even a slightly better error, but not sure why I didn't pick this
22:17
<
apritzel >
mmh, I think we do now know how to calculate the rate, so could revisit some XXX comments in ccu_sdm.[ch]
22:18
<
apritzel >
wens: do you know where your 98285714 comes from?
22:19
<
wens >
seems like the reset default
22:19
<
wens >
ok, probably missing some flag then
22:21
<
apritzel >
are you looking at that MCU audio PLL?
22:24
<
wens >
I'm playing with i2s at the moment, which seems to prefer audio0 pll
22:24
<
wens >
something weird is going on
22:30
<
wens >
ah, right, audio1 rate calculation is somewhat broken
22:45
<
wens >
blah, wrong ops
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