<alyssa>
wondering if simply not building the util/lut test on msvc is unreasonable since I don't expect that code to be used on msvc ever
<alyssa>
(and even in some bizarro future where agx or anv or something builds on Windows, it'd probably be on mingw/clang and not msvc.)
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<mlankhorst>
Yeah curious what a non-accelerating non-modeset device would look like
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<daniels>
mlankhorst: vgem
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<dolphin>
airlied, sima: backmerged drm-next to drm-intel-gt-next to bring in some changes that had been committed via other trees (without acks, too...)
<Leftmost>
Is https://github.com/KhronosGroup/SPIRV-Guide the best place to get started with understanding SPIR-V (with an eye toward contributing to mesa)? Are there other resources that I should look at?
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<jenatali>
alyssa: ack, I don't see a good way around that one either
<alyssa>
jenatali: k, will do that when i'm in the office
<alyssa>
thanks
<alyssa>
We'll probably eventually use that in NIR but in a dedicated opt pass that again can be msvc-gated since you dont need it
<alyssa>
[Folding stuff like `iand(a, ior(b, c))` into `lut3(a, b, c, 0xsomething)`
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<Company>
alyssa: technically, you can add #define a ((uint8_t) 0xAA) in the header or do "static const uint8_t a = 0xAA;" to avoid the gnu extension, but I'm not sure you wanna deal with the side effects of the global symbols
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<lucaceresoli>
Hello, I am a drm-misc committer, but only even committed to drm-misc-next. Can I commit to drm-misc-fixes too?
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<mlankhorst>
Sure
<lucaceresoli>
mlankhorst: ah, thanks! -- Just wanted to make extra sure I'm not committing where not supposed to :)
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<lucaceresoli>
oops, while applying using 'dim b4-shazam' I get:
<lucaceresoli>
-:11: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
<karolherbst>
dj-death: hacking on nir_opt_acquire_release_barriers was kinda what I'd try to do when there is nothing else
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<pendingchaos>
could maybe use ACCESS_COHERENT for ssbo/image instead of make-available if you're okay losing the memory scope
<pendingchaos>
I'm not 100% sure, but make-visible might be slightly different from ACCESS_COHERENT
<pendingchaos>
(make-visible might make future accesses to the same location visible, not just ACCESS_COHERENT's behaviour of only affecting the first access)
<karolherbst>
ohh it also does non atomics mhhh
<karolherbst>
yeah.. only really caring about shared memory atm
<karolherbst>
pendingchaos: yeah, your commit works perfectly
<karolherbst>
I have shaders I want to beat nvidia at, and this problem solved reduces the gap by 12 pp :D
<karolherbst>
but let me see if nir_opt_acquire_release_barriers also helps
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<karolherbst>
yeah so nir_opt_acquire_release_barriers doesn't seem to do anything
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<karolherbst>
well needs an atomic present to operate mhh
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<alyssa>
Company: Uh yeah no we're not dealing with that heh
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<Company>
the other option I thought about is turning it into a static inline constexpr lambda function somehow, but I have no idea if you can abuse MSVC's C++ skills for that
<alyssa>
I thought about that but I don't really want to compile random C code as C++, that's bit me too many times
<Company>
I'd only do that with #ifdef MSVC, but yeah
<jenatali>
Yeah I was contemplating ways to do it with multiple macros, i.e. passing the expression into a second macro which has a, b, c parameters where you can pass constants, and then I think into a third to force expression evaluation?
<jenatali>
Lemme godbolt that and see if it works...
<jenatali>
Seems you can just leak some implementation details of the VK_OUTARRAY macros into an inline function and it's not so bad
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<jenatali>
Better than doing all of that in macros IMO
<dj-death>
the problem is that the structure defined in macros locally
<dj-death>
but okay
<dj-death>
will deal with it :)
<jenatali>
Oof
<jenatali>
Anonymous structs are fun...
<jenatali>
If this was C++ you could just make it a template and pass the anonymous struct type...
<gfxstrand>
alyssa: b2b32 can be whatever representation you want. It exists for shared memory which never leaves the GPU so as long as b2b1 can consume b2b32, you're good.
<alyssa>
gfxstrand: Yes but if you define it any different from NIR, you don't match the constant folding which seems.. really suss.
<alyssa>
In general I think we've nak'd NIR ALU opcodes that change definition based on the backend
<alyssa>
I don't see why this is different
<alyssa>
and also b2b32/b2b1 get emitted for non-shared mem stuff too
<alyssa>
(seemingly including UBOs)
<alyssa>
(and SSBOs)
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<gfxstrand>
alyssa: Uh... It shouldn't be for UBOs/SSBOs. That should be i2b/b2i
<gfxstrand>
We do use b2b for shader/function_temp, though. But again, doesn't escape the GPU.
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<alyssa>
gfxstrand: Uhhhh
<alyssa>
then lower_explicit_io seems to do the right thing but lower_io doesn't
<gfxstrand>
Because `lower_io` shouldn't be used for these things?
<gfxstrand>
and/or should be fixed
<alyssa>
Hm. I definitely saw this in shaderdb yesterday, I'll try to figure out the root cause
<alyssa>
but also - I stand behind my earlier/actual objection of 'NIR ALU opcodes with impl-defined behaviour scare me and we shouldn't be doing them'
<alyssa>
If we genuinely want to change the encoding per-GPU, i'd rather have a shader option that makes lower_explicit_io & friends change what actual opcodes they generate
<alyssa>
(could be wrapped up in helpers to centralize that logic)
<alyssa>
but so far I haven't seen a good reason not to just do 0/~0 everywhere
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<ahadi>
Hi, I'm trying to implement cswr(context save and restore) for amdgpu .. I can see in their amdkfd driver amd make use of sendmsg(MSG_RTN_SAVE_WAVE) which seems to return an address for each wave to write it's gprs and other regisetrs to ? .. but only amdkfd allocate a cswr buffer for this .. I also saw that it has smth to do with MQD(m... queue descriptor ?) .. my quesion is ..
<ahadi>
is this mes specific functionality and amdgpu and mesa doesn't/can't make use of this or it's smth I can make use of if I use debugfs to set priv registers ?
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