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<tzimmermann>
sima, airlied, hi. could you please formward drm-next to -rc6?
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<sima>
tzimmermann, I guess backmerge and do you need something specific? or did you mean drm-fixes?
<tzimmermann>
sima, yeah backmerge. i want to get drm-misc-next and -next-fixes to -rc6
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<sima>
tzimmermann, will look into it later today, going to the gym this morning
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<airlied>
tzimmermann: doing a backmerge at the moment
<airlied>
needed it for msm
<airlied>
tzimmermann: pushed out now
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<tzimmermann>
airlied, thanks
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<jani>
hwentlan__: stumbled on parse_edid_displayid_vrr() and parse_amd_vsdb() etc. in amdgpu_dm.c... why is this being added in the driver, it's all supposed to be in drm_edid.c...
<jani>
and the idea kind of is that drivers don't modify connector->display_info
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<tzimmermann>
PSA: With -rc6 tagged, drm-misc-next-fixes is now open. Features still go into drm-misc-next. Fixes for v6.17 or stable go into drm-misc-fixes. Fixes for v6.18 go into drm-misc-next-fixes. Patches in -fixes branches should be small and have a Fixes tag.
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<sima>
airlied, thx :-)
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<alyssa>
how is b2b32 actually defined?
<alyssa>
is (('ineg', ('b2i32', a)), ('b2b32', a)) legal?
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<pendingchaos>
IIRC b2b1(b2b32(a@1)) == a
<karolherbst>
my gut feeling says yes, but who knows
<alyssa>
pendingchaos: right. that's not strong enough for the rule I'd like
<pendingchaos>
(I could be wrong, I just remember the opcode being added so that the 32-bit value can be some faster but backend specific value)
<alyssa>
right..
<alyssa>
Intel would like an opcode that's actually explicit 0/~0
<alyssa>
so then we can optmize ineg/b2i32 in NIR
<alyssa>
Or maybe the crazier rule this shader could benefit from -- i2i32(unpack_32_4x8(ineg(b2i32(x)).<whatever>)) -> b2b32(x)
<karolherbst>
I wonder if there is hardware that defines those bools differently?
<karolherbst>
afaik nvidia defines them the same as intel
<alyssa>
ac/llvm seems to do 0/1 but could maybe be fixed
<karolherbst>
mhhh
<karolherbst>
could add configurable opts
<jenatali>
HLSL defines 32-bit bools as 0/1, not 0/~0
<pendingchaos>
ACO has always implemented it as 0/1
<pendingchaos>
problem with just "b2b1(b2b32(a@1)) == a" is that it can break if the backend doesn't match constant folding
<alyssa>
jenatali: that's not really relevant. we can opt_algebraic chew thru whatever.
<alyssa>
pendingchaos: yeah, exactly
<karolherbst>
at least on nvidia: 0/-1 and 0.0/1.0
<alyssa>
I don't care what encoding we pick but we should really have one canonical encoding
<alyssa>
in NIR
<alyssa>
because yeah not matching constant folding is.. bad
<alyssa>
and "NIR ops that change behaviour by backend" are.. bad
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<karolherbst>
could make it part of the nir options
<alyssa>
no
<alyssa>
r600/sfn i cant tell at a quick glance what it does
<alyssa>
zink does 0/1
<alyssa>
as does dxil
<alyssa>
as does nak seemingly
<alyssa>
well this a mess.
<karolherbst>
nvidia might have gotten rid of a canonical format in hw
<alyssa>
half the backends do one thing and half do another
<jenatali>
What's constant folding do?
<alyssa>
jenatali: 0/~0
<alyssa>
i think
<jenatali>
Ouch
<karolherbst>
I'm actually curious why nak does 0/1 🙃
<karolherbst>
though I think the hw used to accept anything
<karolherbst>
as long as it's 0 and not 0
<alyssa>
r600/sfn I think does 0/~0 if I'm reading the code right
<alyssa>
it's zink/dxil, aco/ac-llvm, and nak vs everything else
<alyssa>
zink/dxil & nak look trivial to change to 0/~0 with no/minimal perf impact
<alyssa>
amd idk C++ scares me, which is why I work at compilers at Intel -- frick
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<karolherbst>
just port it over to C before touching it, ez
<alyssa>
dont tempt me with a bad time
<karolherbst>
what scares me is, that with you I'm not sure you wouldn't suddently do it
<alyssa>
of note, AGX internally uses 0/1 booleans (it's better for the hw)
<alyssa>
but I still implemented b2b32 as 0/~0 because I thought I had to :)
<alyssa>
seems fine \shrug/
<karolherbst>
so in case it matters, CLC actually defines them as 0/1
<alyssa>
it really doesn't matter what frontends or backends want, it's easy to massage to whatever
<alyssa>
we just need to pick something and be consistent
<alyssa>
pendingchaos: do you have concenrs from an AMD perspective changing to 0/~0?
<alyssa>
gfxstrand: ^ from a nvidia
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<pendingchaos>
b2b32 is faster for uniform booleans because it can use SCC directly
<pendingchaos>
but because we always use b2b32 right before a shared memory store (unless that changed at some point), we would insert a copy to convert to VGPR anyway
<pendingchaos>
for divergent booleans, 0/1 allows a trick with "a + b + b2b32(c)" to use only one instruction, but that's the shared store thing again
<pendingchaos>
so 0/~0 for b2b32 is probably fine
<alyssa>
the `a + b + b2b32(c)` trick being.. add-with-carry instruction?
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<pendingchaos>
yes
<alyssa>
right..
<pendingchaos>
the carry-in is the same representation as divergent booleans
<alyssa>
where is the b2b32 coming from in that case? why is it not a b2i32?
<alyssa>
it's concerning given b2b32 is, currently underdefined it seems
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<pendingchaos>
I'm not sure if that code actually appears, because IIRC b2b32 is only used for shared stores
<pendingchaos>
the carry-in opt was probably made to optimize "a + b + (c ? 1 : 0)" instead, but both look the same to ACO at this point
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<alyssa>
right.. so that should be fixed to only look for b2i32 instead
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<alyssa>
actually the aco opt is already fine
<alyssa>
yeah so all of this to me sounds like "define b2b32 as 0/~0, leave b2i32 as 0/1, fix isel in a few backends, move on"
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<alyssa>
Or.. delete b2b32 altogether and just use bcsel(0, ~0) explicitly
<alyssa>
(and make nir_b2b32 a helper that generates a bcsel)
<alyssa>
similar to what idr did with i2b32 years ago
<alyssa>
also probably delete b2b1 and make it a helper doing ine
<alyssa>
this might require aco's bcsel & ine becoming more clever to avoid regressing codegen for scalar
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<alyssa>
ir3 does a trick with ABSNEG_S which would need replumbed
<alyssa>
all of zink_nir_algebraic would get deleted which is nice
<alyssa>
ok. Yeah I think this is worth doing
<idr>
alyssa: Not to throw a wrench in things...
<alyssa>
/o\
<idr>
I have a branch that I've been poking at from time to time that tries to emit 16-bit Booleans to decrease register pressure.
<alyssa>
Great!
<alyssa>
..So?
<idr>
That ends up producing some b2b32 when a b16 and a b32 would be mixed.
<idr>
I don't know of that would run afoul of what you're thinking of doing.
<idr>
The branch hasn't shown a clear win yet, so... *shrug*.
<alyssa>
idr: My current proposal is simply "remove b2b1 & b2b32 opcodes, systematically convert producers to ine/bcsel, make backend's ine/bcsel smarter to match codegen if needed"
<idr>
Okay. That sounds reasonable.
<idr>
I've been thinking we might want type conversion opcodes in brw, but that's a topic for another day.
<idr>
(Short version: MOV is too flexible. It's a hassle to determine, "Is this just type conversion, or is it doing other regioning nonsense too?")
<alyssa>
Sure. I don't think that has any bearing on the NIR clean up
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<alyssa>
..Ok, NIR trivia question..
<alyssa>
Is ieq valid on 1-bit bools? What about ine?
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<Mis012[m]>
AI likes 1.5bit, Nvidia should really get on that
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<ngcortes>
qq; is there a way to manually reset the gpu when a gpu hang occurs? also, if there are concurrent processes running that are using the gpu, is there a way to "pause" those processes when a gpu reset occurs (ie. after a gpu hang)?