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<junari>
I moved this reset to usb2-phy for now, since usb3-phy has its own reset, and for DWC usb3 this option is optional
<junari>
Do you know if there is any way to run dwc usb3 controller without usb3 phy only with usb2 phy?
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<apritzel>
do you mean for USB 2.0 operation only?
<junari>
yes
<apritzel>
I have no clue, but was thinking about this already, for the Radxa board, where we then could use the USB port at least in USB 2.0 setup, alongside the M.2 slot
<apritzel>
but I think the D-/D+ pins are port of the muxing ...
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<BroderTuck>
apritzel: in your v2 uboot series, you've been inconsistent in how you describe the wifi for the boards. Nothing major since the aic8800 driver isn't (properly) mainlined anyway, just something that could be improved for a v3.
<apritzel>
BroderTuck: what do you mean with WiFi in U-Boot? If you refer to the DTs, that's a verbatim 1:1 cherry-pick of the Linux DTs. Any complaints / patches should go to the Linux lists
<BroderTuck>
junari: seems you are closer to having the usb3 code in a shape ready for upstreaming, looking forward to it. Maybe work together with juanesf93 who works on the pcie side of the equation
<BroderTuck>
apritzel: Mostly just the description portion of the patches
<apritzel>
BroderTuck: what do you mean exactly? The commit messages for the DT patches? Those are done and dusted, in the Linux kernel repository
<BroderTuck>
yes, the "this board/box features:" text, but it's no biggie
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<BroderTuck>
I believe it should be possible to use the pcie in conjuntion with the usb2 part of the usb3 controller
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<apritzel>
BroderTuck: what makes you say so?
<BroderTuck>
1: the datasheet/manual doesn't seem to show the USB2_DM/P pins as being muxable, and the bsp combophy code from the avaota repository talks about a PHY_USE_BY_PCIE_USB3_U2 mode
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<apritzel>
well, AFAICT the USB 2.0 part of the operation is covered by the DWC3 USB3.0 controller (there is apparently no separate EHCI/OHCI pair), so we need to figure out how to limit that to USB 2.0
<apritzel>
(or does that happen automatically, since it can't negotiate with any peer on the disconnected USB3.0 wires?)
<BroderTuck>
I'd guess "automatically", since the port in that cse should just have the usb2 wires
<BroderTuck>
*case
<apritzel>
junari: BroderTuck: do you know where that second USB2.0 PHY is? Is it integrated into the existing USB2.0 PHY, so does that actually have three ports instead of the two we assume?
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<junari>
yes
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<junari>
it's part of usbphy: phy@4100400
<apritzel>
junari: are you sure? I just found "0xC200 Global USB2 PHY Configuration Register" in the USB3 DRD register description, so is the USB2.0 integrated there?
<BroderTuck>
the USB3.1 DRD section of the a527 datasheet says "One USB 2.0 UTMI+ PHY (USB2) \n One USB3.1 PIPE PHY (USB3)"
<apritzel>
yes, and the BSP DT and the manual seem to hint at some extra PHY integrated into the DWC IP: @0x4e00000
<junari>
no, but I added it in there and it works
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<apritzel>
dlan: do I get this right that the Radxa A5E board connects the two USB1 DP/DM pins to the USB type C connector, next to the USB3.0 SuperSpeed pins? So the USB 2.0 part would be handled by the USB1 EHCI/OCHI controller?
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<apritzel>
libv: looks like the wiki is not feeling alright? I got
<dlan>
apritzel: are you talking about the USB type A port (not type C)? the "USB2" in the schematics
<dlan>
and I think it's a 'Yes'
<apritzel>
libv: ... either gateway timeouts or VERY slow connections (to the main page)
<apritzel>
dlan: ah, yeah, sorry, I was just looking at the schematics
<dlan>
the type C is "J2" in schematics, next to ethernet port
<apritzel>
dlan: I wonder how this works? are the D-/D+ and the two SuperSpeed wire pairs really completely independent?
<dlan>
did you check the schematics? page 7
<dlan>
the D-/D+ is USB1-DM/DP
<dlan>
while superspeed pin shared with PCIe
<dlan>
so the GMA340 chip for mux purpose
<apritzel>
yes, that's what I mean: the user manual suggests that USB2 D-/D+ are the USB2.0 pins associated with the USB3.0 controller
<apritzel>
so using USB1 is at least ... unusual
<apritzel>
because an XHCI compliant controller takes care about both USB 2.0 and USB 3.0 transfers
<apritzel>
using USB1 means we can use it today already, since that's the pure and well-known USB 2.0 path. But I wonder how this flies once USB 3.0 comes into play here
<dlan>
oh, I haven't checked user manual..
<apritzel>
I was under the impression that both the HighSpeed and SuperSpeed pins in a USB 3.0 port must be controlled by the same controller - but I could be wrong
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<junari>
У меня получилось примерно 300 строк кода, чтобы заставить USB3 работать
<junari>
Oops, wrong chat
<jakllsch>
WHQL (now) insists that the one XHCI controls both the USB 2 and USB 3 lines on one physical USB connector; but there was a time when even PC motherboards routed the USB2 and USB3 lines of one port to different HCIs
<jakllsch>
(my M4A87TD/USB3 motherboard is one of those that routed them to seperate HCIs)
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<junari>
I will try to send patches for usb3 in the next few days. It turned out to be about 300 lines
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<apritzel>
jakllsch: ah, that's good info, thanks! So is there any kind of handover between USB2.0 and USB3.0? So that the controllers needs to work together at least on the software side? Or can they be completely independent?
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<jakllsch>
apritzel: my understanding is it's up to the device to decide which interface to use
<jakllsch>
so the host controllers can be independent
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<libv>
apritzel: the wiki seems to have fixed itself?
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<apritzel>
libv: indeed, looks good again from here as well
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<apritzel>
... or not, stalling again ...
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