ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<nickchan>
new codenames from ios 26's ane fw: Nevis, Borneo
<nickchan>
soc codenames
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<amarioguy>
so it turns out that the cpu interface not supporting extended spi ranges isn't a roadblock to supporting them period....
<amarioguy>
just saw maz's cursed patchset for that...
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<maz>
amarioguy: which patch set?
<amarioguy>
maz: "irqchip/gic-v3: Warn about inconsistent implementations of extended ranges", commit ad5a78d
<amarioguy>
that seems to just be a warning and define tho, seems to be part of a larger patchset for the gic driver?
<amarioguy>
can't find which series it's a part of unfortunately
<maz>
amarioguy: well, the *emulation* you present to the guest must be consistent. Either you fully support extended ranges (both in the cpuif and dist/rdist), or you don't.
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<amarioguy>
ok so still probably safer to not do ext spi ranges in my emulated distributor - but then we have a different problem, most apple platforms have > 1024 irqs so i'm not sure if i need to compress some irqs to a single intid
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<maz>
it should be fine to expose extended ranges, as long as your dist supports it. in general, the cpuif shouldn't really care about the INTID it reports to the guest (they all have the same state machine), so supporting it should be rather simple (and by that, I mean simple for a GIC feature...).
<amarioguy>
alright makes sense - i kinda thought that at first but wanted to sanity check it
<maz>
I never bothered emulating it in KVM because our VMs tends to only have a small number of SPIs, and use LPIs much more liberally.
<maz>
same thing for PPIs, we're quite happy with only a handful.
<maz>
and GICv3 is soooo last year anyway... ;-)
<amarioguy>
makes sense - i should look at how that works, because my understanding of the GIC documentation led me to believe that you use SPIs for HW not on the PCIe bus and LPIs as a stand-in for MSIs
<amarioguy>
seems like LPIs might be more general based on what you're saying
<maz>
once you start having virtual devices, it's a lot simpler to have MSIs for most of the devices. they scale, and they are simpler to handle.
<maz>
so its not that LPIs are more general, it's mostly that level interrupts as SPIs are a pretty dumb way of injecting virtual events in a VM.