ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<nickchan>
wdt is probably fine to be in first device tree
<nickchan>
i guess i can think about auto generate adt cause doing it for 69 (this is the actual number of pre-M1 skus supported in linux) skus is not fun
<fl0_id>
thx I will take a look again later. I'm very aware that there are still issues, likely I did not conisder the ranges property
<fl0_id>
though I adapted a bit to fit newer style, f.e. using cpu-map
<fl0_id>
and clusters
<nickchan>
that one's style is too old and the one i showed should be fine aside from pinctrl
<nickchan>
Which can be ignored and removed in bringup
<chadmed>
dont we need the 1ghz clock too for m3+?
<fl0_id>
sure. I think I looked at that one too. and very little if anything should be extra. I only though about adding the display, as it's a laptop, but hopfeully framebuffer works without as this needs DART or sth I think
<chadmed>
m1n1 should fill that with the iboot framebuffer which will work with simpledrm
<nickchan>
/chosen/framebuffer should be enough for display
<nickchan>
wdt and serial would help bringup too
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<jannau>
ahdeb[mds]: the `mv -f "$TARGET" "${TARGET}.old"` is unchanged in that commit. using `cp --preserve=timestamps -f` should make the switch atomic. feel free to create a PR
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<jannau>
#address-cells / #size-cells specify the layout of the "reg" property. address-cells = 1, #size-cells = 0 is perfectly valid in some places, for example for i2c devices
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<fl0_id>
nickchan thx, good to know that's what I was hoping. I have serial I think. not sure about wdt
<fl0_id>
jannau thx for explaining
<fl0_id>
nickchan are you sure that "apple,aic" cannot be compatible? while the adt has compatible = [aic,3] for the aic, the wdt has compatible = [wdt,t8101, wdt,s5l8960x]
<fl0_id>
so I assume the s5l8960x is still there
<fl0_id>
(this is from the adt)
<sven>
it’s at least v2 for m3, maybe even v3
<sven>
really, don’t trust the ADT for stuff like compatibles
<sven>
they work differently there
<fl0_id>
ok
<sven>
the adt node e.g. has a version property somewhere
<sven>
I know that v3 introduced some more properties for register offsets but they seems similar to v2
<jannau>
I plan to send that (and the dt-bindings change) after 6.16-rc1\
<jannau>
I would read "aic,3" as "aic3"
<jannau>
iirc the offsets specified in the ADT differ from the aic2 values
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<fl0_id>
makes sense
<fl0_id>
sth else - if there is not just one address and size for a register, is just the first one used for the dt, or is there a more complicated calculation e.g. how a set of five address / size pairs for a reg entry are transcribed?
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