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<wctrl[m]>
oops apparently my message wasn't sent due to missing registration; Is there any requirements for DVFS with mali bifrost besides opp table on the mediatek SoC? clock rate is always the same for me
<robmur01>
IIRC, some MTK SoCs were fiddly because they have multiple regulators, where the generic OPP code only supports one
<robmur01>
however if you do have the appropriate regulator-coupling trickery and an appropriate OPP table with only one set of voltages then I believe that should work, provided you have all the relevant devfreq stuff enabled in your kernel
<wctrl[m]>
hmm only powersave drops to minimal frequency
<wctrl[m]>
lemme check if it'll heat like before
<robmur01>
yeah, nothing looks particularly wrong there - at this point I'd consider something at the clock driver end to be the most likely suspect, especially if the other governors can't change it as expected either
<wctrl[m]>
hm well the clock changes only with performance/powersave governors, and even on 300mhz it's pretty hot
<wctrl[m]>
maybe I messed up voltages
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<wctrl[m]>
hmm yeah sram voltage is bigger than expected (while freq is 300mhz the voltage is for 768mhz), ideas how i can set voltage map between coupled regulators?