ChanServ changed the topic of #lima to: Development channel for open source lima driver for ARM Mali4** GPUs - Kernel driver has landed in mainline, userspace driver is part of mesa - Logs at https://oftc.irclog.whitequark.org/lima/
<sarbes>
If I had the time...
<sarbes>
But I have some coming up.
<sarbes>
Thanks for confirming.
<anarsoul>
OK, I'm bisecting it
<anarsoul>
shouldn't take longer than 15mins, it's only 11 steps
<anarsoul>
40497ca3a907e734b2dab95c83540bb7bfec14dc is good
<anarsoul>
it sounds like it's a bug in printing the shader though, because it's compiled just fine
<anarsoul>
7b70b419b5282fb01b7202e5ee1d391fcba15ef8 is the first bad commit
<anarsoul>
yeah, reindexing SSAs fucks up the registers :)
<anarsoul>
likely a bug in ppir_add_write_after_read_deps()
<anarsoul>
nah, it's a bug in translation
<anarsoul>
I vaguely remember that ppir expect regs indices to start after all SSA indices
<anarsoul>
I only tested it with shaders/chromeos/24.shader_test
<anarsoul>
nah, it's actually wrong
<anarsoul>
we need to shift SSAs instead
<anarsoul>
well, you've got the idea, so I bet you can fix it :)
<anarsoul>
the problem is the way we are tracking writes to individual channels of the registers. There might be up to 4 nodes, while an SSA is always 1
<anarsoul>
so comp->var_nodes size is x4 of number of nir defs
<anarsoul>
we need to do the math properly when fetching a node for SSA or for the register
<anarsoul>
currently it's broken. It was kind of relying on nir defs indices for reg definitions to start after all the SSA indices
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